Dtmf Remote Appliance Control System Using Mobile Phone

CHAPTER 1 INTRODUCTION This project DTMF REMOTE APPLIANCE go over brass USING ready PHONE is utilize to cook appliances which argon outside(a) keep in line away from the user employ supple ph bingle. The aim of the proposed frame is to fracture a price effective solution that forget run tyrannical of dwelling house appliances remotely and enable home security a wearst intrusion in the absence of homeowner. The bends committed as home and falseice appliances consume galvanisingal originator and they should be find outled as well as turn on /off if compulsory. Most of the snip, it was done manu bothy.Now it is a necessity to mold devices more effectively and efficiently at what invariably quantify from some(prenominal)where. Take an instant when we ar going to office and suddenly remembered that to switch off the micro shudder oven we aviate convenient if we could switch off without going back to home, in such(prenominal) situations this project comes t o our rescue. In this system, we ar going to develop a cellular phone based home/office appliance go steadyler for lordly ar pussyrary devices. This take ons a fluid phone which is machine-accessible to the system via whirl treated.To activate the diligent phone unit on the system, a key out is to be made and as the claim is answered (auto answer humor), in reaction the user would enter a password to soprieve the system to verify devices. As the dealer contendes the precise but long ton on the keypad, it results in turn ON or by specific device and the device chemise is achieved by relays. In this project, we knowing a basic sense modalityl and it is utilise to maneuver 4 lights using a mobile phone, micro- seeler and transceiver. The maximum takings of devices that preserve be ope treasured allow for be the number of buttons establish on the keypad of mobile phone. . 1 Block plot design 1. 1 Block diagram Fig 1. 1 re give ways the block diagram of DTM F removed Appliance attend System using Mobile phone, utilise to check the appliances presend at a distance. Brief comment of Hardw atomic number 18 Modules The DTMF remote Appliance Control System consists of 1. Mobile Phone 2. MT8888 DTMF Transceiver 3. Philips 89C51 Micro- inhibitler 4. Liquid watch glass introduction 5. antecedent Supply Unit 6. relay race Driver 7. Relays 8. Devices 1. 2. 1 Mobile Phone Mobile Phone is apply as a media to instruct the micro controller to agent ON/OFF the appliances.The mobile phone use here is Nokia 6030 as it has the required features and is interfaced with the transceiver finished ear phones. 1. 2. 2 MT8888 DTMF Transceiver The MT8888C is a monolithic DTMF transceiver with previse extend up dribble. The transceiver consists of vector and adoptr. The DTMF intercommunicates ar genetic through with(predicate) communicateter and they atomic number 18 received by the mobile phone and de work outd using a DTMF receiver/de f igurer ICs. 1. 2. 3 PHILIPS 89C51 Micro Controller The PHILIPS 89C51 is a deplorable cost micro-controller.It has a 40 immobilise con describeu balancen and contains non volatile Flash memory of 64KB which is approximately(prenominal) parallel of latitude curriculummable and straight publication in system platformmable memory. 1. 2. 4 liquid quartz glass divulge display The liquid crystal display unit receives office statutes (8 poker chips per roughage) from a microprocessor or microcomputer, latches the codes to its display information pound off (80 byte DD motor for storing 80 display themes), transforms all(prenominal) grammatical case code into a 5&2157 dot matrix cause pattern, and displays the characters on its liquid crystal display screen. 1. 2. 5 might Supply Unit The causality emerge unit is used to stand a constant 5V tack on to assorted ICs.This is a standard go using foreign 12V DC adapter and headstrong 3- pivot potency regulator. Dio de is added in series to avoid reverse potency. 1. 2. 6 Relay Driver The ULN2003 is a exalted- voltage, exalted- received darling ton device device driver comprising of vii NPN darling ton pairs. For high enter ohmic resistance, we may use cardinal junction transistors to form a darling ton pair and this pair in CC configuration provides introduce impedance as high as 2Mohms. 1. 2. 7 Relays Relays argon remote control electrical switches that ar controlled by an otherwise switch, such as a horn switch or a computer as in a originator twine control module.Relays al blue a small current f up garb lot to control a high current set. 1. 2. 8 Devices The devices burn be micro-wave oven, bulbs, fans, air cooler, and so onwhich be far away from the user. The micro-controller plays the intelligent part in tyrannical these devices. 1. 3 Working This project is used to control the appliances present at a distance using a mobile phone. The basic note is the user should ma ke a beseech to the mobile phone, which is in auto answer regularity and thus shriek gets committed. The user presses the forms present over the keypad of his phone for controlling the appliances present at home or office.Whenever a button is pressed a ghost is generated and it is exilered to the mobile phone present in the home or office, which is interfaced with the DTMF transceiver. The DTMF receiver decodes the timberland generated and it activates the controller fit inly. The controller operates the devices accord to the cryptograph set by the user. The lieu of the devices whether they be ON/OFF is indicated in the liquid crystal display. CHAPTER 2 MT8888 DTMF TRANSCEIVER debut The MT8888C is a monolithic DTMF transceiver with prefigure progress fall into place. It is fabricated using CMOS technology and it offers low power consumption and high reliability.The receiver section is based upon the patience standard MT8870 DTMF receiver, bandage the transmitter ut ilizes a switched electrical capacity D/A convertor for low deviance, high accuracy DTMF tapering. Internal prognosticates provide a crack sense modality such that bank bill of voice bursts stomach be transmitted with tiny timing. A holler out progress filter butt joint be distinguished allowing a microprocessor to analyze rallying cry progress shadinesss. The MT8888C utilizes an Intel micro interface, which allows the device to be mergeed to a number of popular microcontrollers with minimal foreign system of system of logic.The applications of DTMF transceiver take on credit card systems, paging systems, repeater systems, interconnector dialers, mobile radio and in-person computers. In our project, it is used for decoding the life of voice generated by the user when he presses a button of the keypad. After decoding the tone, it is presumptuousness to the microcontroller for controlling the appliances. Features The features of MT8888 DTMF transceiver include 20 gloaming DIP package Central office persona DTMF transmitter/receiver Low power consumption mellow belt along Intel micro interface Compatible with 6800 microprocessorsAdjus panel guard meter auto preventiveing(prenominal) tone burst mode bellow progress tone spotting up to -30dbm Microprocessor port peg Diagram &038 translation record 2. 1 DTMF bowling pin Diagram digit 2. 1 shows the control stick diagram of MT8888 and the verbal description of the monolithic IC is as shown in the following table 2. 1. circuit card 2. 1 Description of Pins of DTMF Transceiver Pin NoNameDescription 1IN+Non-inverting op-amp arousal 2IN-Inverting op-amp input. 3GSGain require. tumbles access to outturn of await end differential amplifier for connection of feedback resistor. 4VrefReference emf turnout (VDD/2). VSSGround (0V). 6OSC1DTMF quantify/oscillator input. pertain a 4. 7M? resistor to VSS if crystal oscillator is used. 7OSC2Oscillator output. A 3. 579545 MHz crystal connected between OSC1 and OSC2 completes the national oscillator circuit. Leave open circuit when OSC1 is driven foreignly. 8TONEOutput from midland DTMF transmitter. 9WR indite microprocessor input. TTL compatible. 10CSChip distinguish input. Active Low. This bless must(prenominal) be qualified immaterially by make do latch enable (ALE) signal. 11RS0 learn Select input. TTL compatible. 12RDRead microprocessor input. TTL compatible. 3IRQ/CPInterrupt Request/Call Progress (open drain) output. In prevent mode, this output goes low when a sensible DTMF tone burst has been transmitted or received. In address progress mode, this spliff lead output a rectangular signal slighton of the input signal apply at the input op-amp. The input signal must be within the bandwidth limits of the gossip progress filter. 14-17D0-D3Microprocessor info Bus. High impedance when CS=1or RD=1. TTL compatible. 18EStEarly Steering output. Presents logic high once the digital algorithm has observe a valid tone pair (signal condition). whatsoever momentary loss of signal condition will perk up ESt to consequence to a logic low. 19St/GTSteering Input/Guard Time output (bidirectional). A voltage greater than V ts detected at St causes the device to demo the detected tone pair and updated output latch. A voltage less than V tst frees the device to presume a overbold tone pair. The GT output acts to determine the external steering time-constant its state is a consort of ESt and the voltage on St. 20VDDPositive power supply (5V classifiable). 2. 4 Functional DescriptionThe MT8888C unified DTMF Transceiver consists of a high performance DTMF receiver with an national gain telescope amplifier and a DTMF arising which employs a burst counter to synthe size of it precise tone bursts and pauses. A see progress mode can be selected so that frequencies within the specified pass band can be detected. The Intel micro interface allows microcontrollers, such as the 8080 , 80C31/51 and 8085, to access the MT8888C intimate presents. The block diagram of DTMF transceiver is as shown in pulp 2. 2. Figure 2. 2 Block Diagram of DTMF Transceiver 2. 5 Call Progress FilterA call progress mode using the MT8888C can be selected allowing the signal detection of various tones, which identify the progress of a telephone call on the ne 2rk. The call progress tone input and DTMF input ar commons however call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be detected if CP mode has been selected. Figure 2. 3 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the accept bandwidth limits of the filter are hard limited by a high gain comparator with the IRQ/CP pin serving as the output.The square wave output obtained from the Schmitt introduction can be analyzed by a microprocessor or counter ar vagabondment to determine the nature of the call progress tone be detected. Frequencies which are in the reject area will not be detected and consequently the IRQ/CP pin will remain low. Figure 2. 3 Call Progress Response 2. 6 DTMF generator The DTMF transmitter diligent in the MT8888C is capable of generating all sixteen standard DTMF tone pairs with low aberration and high accuracy. All frequencies are derived from an external 3. 579545 MHz crystal.The curved waveforms for the individual tones are digitally synthesized using row and column coursemable rail-splitters and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To ascribe a DTMF signal, selective information conforming to the encoding format shown in slacken 2. 2 must be scripted to the transmit selective information bill. melodic breed that this is the same as the receiver output code. The individual tones which are generated (f poor and f HIGH) are referr ed to as Low conclave and High classify tones.As seen from the table, the low host frequencies are 697, 770, 852 and 941 Hz. The high sort frequencies are 1209, 1336, 1477 and 1633 Hz. Typically the high pigeonholing to low throng amplitude ratio (twist) is 2 dB to compensate for high group attenuation on long cringles. The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During draw up surgical carrying into actions to the Transmit Data tape the 4 spot selective information on the trustworthy deal is latched and converted to 2 of 8 coding for use by the computer computer programmemable divider circuitry.This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a specify neural im split second is issued and the counter pouchs again. The number of time segments is fixed at 32 however, by varying the segment length as describe preceding(prenominal) the frequency can as well be varied. The divider output filaree another counter, which addresses the sine wave lookup enjoin-only memory. accede 2. 2 DTMF Tones FLOWFHIGHDIGITD3D2D1D0 697120910001 697133620010 697147730011 770120940100 770133650101 770147760110 852120970111 52133681000 852147791001 941133601010 9411209*1011 94114771100 6971633A1101 7701633B1110 8521633C1111 9411633D0000 punctuate 0= LOGIC LOW, 1= LOGIC HIGH The lookup table contains codes which are used by the switched capacitor D/A converter to obtain disc drenche and highly accurate DC voltage takes. ii identical circuits are employed to kick upstairs row and column tones, which are and so mixed using a low noise summing amplifier. The oscillator exposit indigences no start-up time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burs t accuracy.A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 2. 4 that the distortion products are very low in amplitude. Figure 2. 4 Spectrum spell 2. 7 Receiver Section Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of 2 sixth-order switched capacitor band pass filters, the bandwidths of which discip telephone line to the low and high group frequencies. These filters incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection.Each filter output is followed by a star order switched capacitor filter section, which smoothes the signals prior to limiting. contain is performed by high-gain comparators which are provided with hysterics to prevent detection of unwanted low-level signals. The outputs of the comparators provide replete rail logic swings at the frequencies of the inbound DTMF signals. spare-time activity the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies.A complex averaging algorithm protects against tone simulation by extraneous signals such as voice speckle providing tolerance to small frequency deviations and transmutations. This averaging algorithm has been developed to ensure an optimal combination of immunity to talk-off and tolerance to the battlefront of interfering frequencies (third tones) and noise. When the detector recognizes the presence of twain valid tones (this is referred to as the signal condition in few industry specifications) the Early Steering (ESt) output will go to an wide-eyed awake state.Any subsequent loss of signal condition will cause ESt to assume an inactive state. The DTMF keypad is as shown in calculate 2. 5 Figure 2. 5 Typical DTMF Keypad 123A697 Hz 456B770 Hz 789C852 Hz *0D941 Hz 1209 Hz1336 Hz1477 Hz1633 Hz 2. 8 Burst styl e In certain telephony applications it is required that DTMF signals organism generated are of a specific continuance determined each by the contingent application or by any one of the exchange transmitter specifications currently existing. well-worn DTMF signal timing can be accomplished by make use of the Burst Mode.The transmitter is capable of issuing symmetric bursts/pauses of predetermine duration. This burst/pause duration is 51 ms 1 ms, which is a standard interval for auto dialer and central office applications. After the burst/pause has been issued, the appropriate rubbish is set in the circumstance study indicating that the transmitter is shit for more information. The timing described above is unattached when DTMF mode has been selected. However, when CP mode (Call Progress mode)is selected, the burst/pause duration is duple to 102 ms 2 ms.Note that when CP mode and Burst mode pretend been selected, DTMF tones may be transmitted only and not received. In a pplications where a non-standard burst/pause time is desirable, a software program timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and crippling the transmitter. Microprocessor interface The MT8888C incorporates an Intel microprocessor interface which is compatible with fast versions (16 MHz) of the 80C51. No wait cycles need to be inserted. Figure 2. 6 and Figure 2. are the timing diagrams for the Intel 8031, 8051 and 8085 (5 MHz) microcontrollers. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS is generated. Figure 2. 8 summarizes the connection of these Intel processors to the MT8888C transceiver. Figure 2. 6 8031/8051/8085 Read time Diagram Figure 2. 7 8031/8051/8085 preserve Timing Diagram Figure 2. 8 MT8888C Interface Connections for Various Intel Micros The microprocessor interface provides access to five intragroup testifys.The contain-only Receive Data cross- bear down contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated. Transceiver control is accomplished with 2 control registers (see turn off 2. 3 and instrument panel 2. 4), CRA and CRB, which select the same address. A write operation to CRB is punish by head start setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA.The read-only military position register indicates the current transceiver state (see Table 2. 5). Table 2. 3 Control Register A Description BITNAME comment b0TOUTTone Output Control. logical system high enables the tone output a logic low turns the tone output off. This bit controls all transmit tone spots. b1CP/DTMFCall Progress or DTMF Mode Select. A logic high enables the receive call progress mode a log ic low enables DTMF mode. In CP mode a rectangular wave representation of the received tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (Control Register A,b2=1).In order to be detected, CP signals must be within the bandwidth specified in the AC Electrical Characteristics for Call Progress. Note DTMF signals cannot be detected when CP mode is selected. b2IRQInterrupt Enable. A logic high enables the disturb ladder a logic low when any 1) a valid DTMF signal has been received for a valid guard time duration, or 2) the transmitter is ready for more info (burst mode only). b3RSELRegister Select. A logic high selects control register B for the next write cycle to the control register address.After writing to control register B, the following control register write cycle will be directed to control register A. Table 2. 4 Control Register B Description BITNAME DESCRIPTION b0 BURSTBurst Mode Select. logic high de-activates burst mode a logic low enables bu rst mode. When activated, the digital code representing a DTMF signal can be written to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51msec). Following the pause, the status register will be updated (b1-Transmit Data Register Empty) and an recess will occur if the interrupt mode has been enabled.When CP mode (control register A, b1) is enabled the rule tone burst and pause durations are extended from a typical duration of 51msec to 102 msec. When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (control register A, b0). b1TESTTest Mode Control. Logic high enables the rivulet mode a logic low de-activates the test mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the signal present on the IRQ/CP pin will be analogous to the state of the curbed steering bit of the status register. 2 S/DSingle or Dual Tone Generation. Logic high selects the si ngle tone output a logic low selects the dual tone output. The single tone generation function registers still selection of either the row or column tones (Low or high group) through the C/R bit (control register B,b3). b3 C/RColumn or Row tone select. Logic high selects a column tone output, a logic low selects a row tone output. This function is used in conjunction with the S/D bit (control register B, b2). Table 2. 5 Status Register Description BITNAMESTATUS OF FLAGSTATUS FLAG unclutter 0IRQInterrupt has occurred. Bit one (b1) or bit two (b2) is set. Interrupt is inactive. open later status register is read. b1Transmit information register empty(Burst Mode only)Pause duration has terminated and transmitter is ready for refreshing information. percipient after Status Register is read or when in non-burst mode. b2Receive Data Register FullValid data is in the Receive Data Register. Cleared after Status Register is read. b3 Delayed SteeringSet upon the valid detection in th e absence of a DTMF signal. Cleared upon the detection of a valid DTMF signal.A software reset must be include at the line of all programs to initialize the control registers upon power-up or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers. The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon ecesis of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a square wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor. 2. DTMF Registers and initialization The DTMF has two control registers, one transmits register, one receives register, and one status register. Along with this at that place is a data dampen which is the entry point for the data for the DTMF to communicate with the microcontroller depending upon the give control signals on the DTMF control pins like rs0,r/w, and the data from the data buffer is communicated with the DTMF. The combination of rs0 and r/w pins will give the following result as shown in table 2. 6. Table 2. 6 DTMF Internal Registers RS0R/WFUNCTION 00Write to Transmit Data Register 1Read from Receive Data Register 10Write to Control Register 11Read from Status Register Initialization of DTMF A software reset must be included at the beginning of all programs to initialize the control registers after power up. The initialization procedure should be implemented 100ms after power up. Description Control Data CS RS0 R/W b3 b2 b1 b0 Read status register 0 1 1 x x x Write to control register 0 1 0 0 0 0 0 Write to control register 0 1 0 0 0 0 0 Write to control register 0 1 0 1 0 0 0 Write to control register 0 1 0 0 0 0 0 Read status register 0 1 1 x x x x Transmission using DTMFThe DTMF has to receive a command to transmit and then the data to send. Consider an example of sending a 50 ms tone- 50 ms pause burst. The procedure is as follows. CS RS0 R/W b3 b2 b1 b0 1. Write to Control Register A 0 1 0 1 0 0 1 (Tone out, DTMF, IRQ, Select Control Register B) 2) Write to Control Register B 0 1 0 0 0 0 0 (Burst mode) 3) Write to Transmit Data Register 0 0 0 0 1 1 1 ( give a digit 7)Reception using DTMF Reception is carried out by checking the status of DTMF for a valid data in receive register and then receive it by a command. The procedure is as follows. 1) Read the Status Register 0 1 1 x x x x -if bit 1 is set, the Tx is ready for the next tone, in which case Write to Transmit Register 0 0 0 0 1 0 1 (Send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case. Read the Receive Data Register 0 0 1 x x x -if both bits are set Read the Receive Data Register 0 0 1 x x x x Write to Transmit Data Register 0 0 0 0 1 0 1 Thus the initialization of DTMF Transceiver is done using the informal registers according to ur requirements and then it is used for decoding the tones generated by the user. CHAPTER 3 THE MICROCONTROLLER 3. 1 Introduction Phillips 89C51 contains a non-volatile tinny program memory that is both parallel programmable and ensuant in system and in application programmable.It is an 8-bit micro controller from MHS-51 Intel family with 4K bytes of scoot and 128 bytes of indwelling RAM. It has 40-pin configuration and it takes input from the external starting times and routes them to the appropriate devices as programmed in it. Features The features of PHILIPS 89C51 include 80C51 Central Processing Unit On-chip FLASH design reminiscence Speed up to 33 MHz Fully Static work RAM expandable externally up to 64 Kbytes Four interrupt priority levels Six interrupt sources Four 8-bit I/O ports Full-duplex heighten UART human body error detection Automatic address recognitionPower Control Modes Clock can be stopped and resumed Idle Mode Power down Mode weapons platformmable clock out Second DPTR register Asynchronous sort Reset Watchdog Timer Pin Diagram &038 Description VCC Supply voltage. GND Ground. bearing 0 carriage 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can adjudicate eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. porthole 0 may excessively be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification. Figure 3. 1 Pin Diagram of 89C51 Micro Controller Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source 4 TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source c urrent (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during f and so ones from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX DPTR).In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 finical Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verifica tion. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs.As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below Port 3 also receives some control signals for Flash programming and verification. The alternate functions of Port 3 are as shown in table 3. 1. Table 3. 1 jumpstart Functions of Port 3 Port PinAlternate Functions P3. 0RXD(serial input port) P3. 1TXD(serial output port) P3. 2INT0(external interrupt 0) P3. 3INT1(external interrupt 1) P3. 4T0(Timer 0 external interrupt) P3. 5T1(Timer 1 external interrupt) P3. WR(external data memory write strobe) P3. 7RD(external data memory read strobe) RST Reset input. A high on this pin for two machine cycle s while the oscillator is running resets the device. ALE/PROG Address bolt Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clock purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external death penalty mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated epitome each machine cycle, except that two PSEN activations are ski pped during each access to external data memory. EA/VPP External Access Enable.EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for part that require12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock in operation(p) circuit. XTAL2 Output from the inverting oscillator amplifier.Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 3. 2. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected w hile XTAL1 is driven . thither are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but borderline and maximum voltage high and low time specifications must be observed.Figure 3. 2 Crystal Oscillator Architecture of PHILIPS 89C51 The architecture of PHILIPS 89C51 is as shown in figure 3. 3 below and the modes of operation include idle mode and power down mode. Idle Mode In idle mode, the processor puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unaltered during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be say that when idle is terminated by a hardware reset, the device ordinarily resumes program execution, from where it left off, up to two machine cycles before the internal reset algorith m takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unpredicted write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Figure 3. 3 Architecture of PHILIPS 89C51 Micro-controller Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and modified Function Registers retain their values until the power-down mode is terminated. The only red ink from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Table 3. 2 Idle and power down modes ModeProg ram MemoryALEPSENPORT0PORT1PORT2PORT3 IdleInternal11DataDataDataDataIdleExternal11FloatDataAddressData Power downInternal00DataDataDataData Power downExternal00FloatDataDataData Timer 0 and Timer 1 The Timer or antagonistic function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters swallow four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. Memory Organization During the runtime, micro controller uses two different types of memory one for holding the program being executed (ROM memory), and the other for temporary storage of data and auxiliary variables (RAM memory).Depending on the particular model from 8051 family, this is usually few kilobytes of ROM and 128/256 bytes of RAM. This amount is built-in and is competent for common tasks performed independently by the MCU. However, 8051 can address up to 64KB of external memory. CHAPTER 4 S ERIAL COMMUNICATION 4. 1 Introduction When a micro processor communicates with the outside world, it provides data in byte-size chunks. In some cases, such as printers, the information is simply grabbed from the 8bit data bus of the printer. This can work only if the cable is not too long, since long cables diminish and ever distort signals.Furthermore, an 8-bit data path is expensive. For these reasons, serial communication is used for ravishring data between two systems located at distances of hundreds of feet to millions of miles apart. The fact that in serial communication a single data line is used kinda of the 8bit data line of parallel communication makes it not only a great deal cheaper but also makes it possible for two computers located in two different cities to communicate over the telephone. Serial data communication uses two methods, asynchronous and synchronous.The asynchronous method transfers a block of data at a time while the synchronous data transfers a single byte at a time. It a mean possible to write software to use either of these methods, but the programs can be tedious and long. For this reason, there are special IC chips made by some manufacturers for serial data communications. This chips are commonly referred to as UART (Universal Asynchronous Receiver Transmitter) and USART (Universal cooccurring Asynchronous Receiver Transmitter). The ARM has built in UARTs. Figure 4. 1 Serial Communication 4. Asynchronous Serial Communication &038 Data inclose The data coming in at the receiving end of the data line in a serial data transfer is all 0s and 1s it is difficult to make sense of data unless the sender and receiver agree on a set of rules, a protocol, on how the data is packed, how many bits constitute the character, and when the data begins and ends. produce and bust bits Asynchronous serial data communication is widely used for character orientation transmissions. In the asynchronous method, each character is placed in bet ween start and stop bits. This is called framing.In data framing for asynchronous communications, the data, such as ASCII characters, are packed in between a start bit and a stop bit. The start bit is continuously one bit but the stop bit can be one or two bits. The start bit is always a 0 and the stop bit is 1. Parity bit In some systems in order to maintain data integrity, the relation bit of the character byte is included in the data frame. This means that for each character we have a single parity bit in addition to start bit and stop bits. The parity bit is odd or even. In case of an odd parity bit the number of data bits including parity bit is even.Data transfer rate The rate of data transfer in serial data communication is stated in bps(bits per second). some other widely used terminology for bps in baud rate. baud rate is defined as the number of signal changes per second. As far as the conductor wire is concerned, the baud rates as bps are the same. Data framing Figur e 4. 2 Data Framing 4. 3 RS232 Standard To allow compatibility among the data communication equipment made by various manufacturers an interfacing standard called RS232, was set by the Electronic Industries Association (EIA) in 1960.RS232 is the most widely used serial input-output interfacing standard. In RS232, a 1 is represented by -3 to -25v, while a 0 bit is +3 to +25v. To connect any RS232 to a micro controller, voltage converters such as MAX232 are used. Max 232 IC chips are commonly referred to as line drivers. RS232 connectors The RS232 connector is as shown in figure 4. 3 and the working of pins is described in table 4. 1 Figure 4. 3 RS232 Connector Table 4. 1 Pin description of RS232 Connector Pin noFunction 1CD-Carrier Detector 2RxD-Receive Data 3TxD-Transmit Data DTR-Data Terminal Request 5GND-Signal Ground 6DSR-Data Set Ready 7RTS-Request To Send 8CTS-Clear To Send 9RI-Ring Indicator MAX 232 The RS 232 is not compatible with microcontroller, so a line driver converts t he RS 232s signals to TTL voltage levels. The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply transient ischemic attack/EIA-232-F voltage levels from a single 5v supply. Each receiver converts TIA/EIA-232-F inputs to 5v TTL/CMOS levels. These receivers have a typical threshold of 1. 3v, a typical hysteresis of 0. v, and can accept 30v inputs. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. Transfer between microcontroller and RS 232c Figure 4. 4 RS232 Level to TTL Level Conversion CHAPTER 5 LIQUID crystallization DISPLAY 5. 1 Introduction The liquid crystal display unit receives character codes (8 bits per character) from a microprocessor or microcomputer, latches the codes to its display data RAM (80-byteDD RAM for storing 80 characters), transforms each character code into a 5&2157 dot matrix character pattern, and displays the characters on its liquid crystal display screen.The LCD unit incorporates a character genera tor ROM which produces 160 different 5&2157 dot-matrix character patterns. The unit also provides a character generator RAM (64 bytes) through which the user may define up to eight additional 5&2157 dot matrix character patterns, as required by the application. To display a character, positional data is sent via the data bus from the microcontroller to the LCD unit, where it is written into the instruction register. A character code is then sent and written into the Data register. The LCD unit displays the corresponding character pattern in the specified position.The LCD unit can either increment or decrement the display position automatically after each character entry, so that only successive characters codes need to be entered to display a continuous character string. The display/ pointer careen instruction allows the entry of characters in either the left-to-right or right to left direction. 5. 2 Features The features of liquid crystal display include Interface with either 4-bi t or 8-bit microprocessor. Display data RAM. 80 x8 bits (80 characters). Character generator ROM 160 different 5 x7 dot-matrix character patterns. Character generator RAM. different user programmed 5 x7 dot-matrix patterns. Display data RAM and character generator RAM may be accessed by the microprocessor. Numerous instructions. Clear Display, cursor Home, Display ON/OFF, Cursor. ON/OFF, Blink Character, Cursor Shift, Display Shift. built-in reset circuit is triggered at power ON. 5. 3 Pin diagram Figure 5. 1 LCD Pin Diagram 5. 4 Pin description VCC, VSS and VEE While VCC and VSS provide + 5 V on and ground, respectively, VEE is used for controlling LCD contrast. RS register select There are two very important registers inside LCD. The RS pin is used for their selection as follows.Is RS= 0, the instruction command code register is selected, allowing the user to send a command such as clear display, Cursor at home, etc. if RS=1 the data register is selected, allowing the user to sen d data to be displayed on the LCD. R/W read/write R/W input allows the user to write information to the LCD or read information from it. R/W=1 when reading R/W=0 when writing. E enable The LCD to latch information presented to its data pins uses the enable pin. When data is supplied to data pins, a high to low pulse must be applied to this pin in order for the LCD to latch in the data present at the data pins.This pulse must be a minimum of 450 ns wide. D0-D7 The 8-bit data pins, D0-D7, are used to send information to the LCD or read the contest of the LCD internal registers. To display letters and numbers, we send ASCII codes for the letters A-Z, a-z, and numbers 0-9 to these pins while making RS=1. We also use RS= 0to check the busy flag bit to see if the LCD ready to receive. The busy flag isD7 and can be read when R/W=1 and RS= 0, as follows if R/w=1 and RS = 0. When D7 =1, the LCD is busy taking care of internal operations and will not accept any new information. WhenD7=0, the LCD is ready to receive new information. . 5 LCD Commands The commands given to the LCD are as shown in table 5. 1 Table 5. 1 LCD Commands enchantREGISTER 01Clear display screen 02Return home 04Decrement cursor (shift cursor to left) 06Increment cursor (shift cursor to right) 05Shift Display right 07Shift display left 08Display off, cursor off 0ADisplay off, cursor on 0CDisplay on, cursor off 0EDisplay on, cursor blinking(a) 0FDisplay on, cursor blinking 10Shift cursor position to left 14Shift cursor position to right 18Shift the unblemished display to the left 1CShift the entire display to the right 80Force cursor to beginning of 1st lineC0Force cursor to beginning of 2nd line 382 lines and 5&2157 matrix 5. 6 Power Supply Unit The input to the circuit is applied from the modulate power supply. The a. c. input i. e. , 230V from the mains supply is step down by the transformer to 12V and is fed to a rectifier. The output obtained from the rectifier is a pulsating d. c voltage. So in order to get a pure d. c voltage, the output voltage from the rectifier is fed to a filter to remove any a. c components present even after rectification. Now, this voltage is given to a voltage regulator to obtain a pure constant dc voltage. Figure 5. Power Supply Unit 5. 6. 1 Transformer Usually, DC voltages are required to operate various electronic equipment and these voltages are 5V, 9V or 12V. merely these voltages cannot be obtained directly. Thus the a. c input available at the mains supply i. e. , 230V is to be brought down to the required voltage level. This is done by a transformer. Thus, a step down transformer is employed to decrease the voltage to a required level. 5. 6. 2 Rectifier The output from the transformer is fed to the rectifier. It converts A. C. into pulsating D. C. The rectifier may be a half wave or a full wave ectifier. In this project, a bridge rectifier is used because of its merits like good stability and full wave rectification. 5. 6. 3 Filter C apacitive filter is used in this project. It removes the ripples from the output of rectifier and smoothens the D. C. Output received from this filter is constant until the mains voltage and clog is maintained constant. 5. 6. 4 Voltage governor As the name itself implies, it regulates the input applied to it. A voltage regulator is an electrical regulator designed to automatically maintain a constant voltage level.In this project, power supply of 5V and 12V are required. In order to obtain these voltage levels, 7805 and 7812 voltage regulators are to be used. The world-class number 78 represents positive supply and the numbers 05, 12 represent the required output voltage levels. Three-Terminal Voltage Regulator Fig 5. 3 shows the basic connection of a three-terminal voltage regulator IC to a load. The fixed voltage regulator has an unregulated dc input voltage, Vi, applied to one input terminal, a regulated output dc voltage, Vo, from a second terminal, with the third terminal con nected to ground.For a selected regulator, IC device specifications list a voltage divagate over which the input voltage can vary to maintain a regulated output voltage over a range of load current. The specifications also list the amount of output voltage change resulting from a change in load current (load regulation) or in input voltage (line regulation). GND4 Figure 5. 3 Fixed Positive Voltage Regulator CHAPTER 6 RELAY DRIVER, RELAYS &038 DEVICES 6. 1 Introduction The ULN2003 is a high-voltage, high-current darling ton driver comprising of seven NPN darling ton pairs. For high input impedance we may use two ransistors to form a Darlington pair. This pair in CC configuration provides input impedance as high as 2Mohms. The input signal varies with the base current of the prototypal transistor this produces variation in the collector current in the first transistor. The emitter load of the first stage is the input resistance of the second stage. The emitter current of the first t ransistor is the base current of the second transistor. The IC is as shown in figure 6. 1. . Figure 6. 1 ULN2003 Relay driver 6. 2 Features The features of ULN2003 relay driver are Output current (single output) 500mA MAXHigh sustaining voltage output 50v MIN Output clamp diodes Input compatible with various types of logic 6. 3 Pin Diagram &038 Description Fig 6. 2 Pin diagram of ULN 2003 The IC is of 16-pin and is a monolithic linear IC. It has 7darlington pairs internally of 7 inputs and 7 outputs i. e. 1 to 7 are inputs of Darlington pairs and 10 to 16 are the outputs, 8-pin is ground and 9-pin is common freewheeling diode. Applications The ULN 2003 driver is used in Relays rooster Lamps Display (LED) drivers 6. 4 Relays 6. 4. 1 Introduction The relay is a device that acts upon the same fundamental principle as the solenoid.The difference between a relay and a solenoid is that a relay does not have a movable core (plunger) while the solenoid does. Where multiple relays are used, several circuits may be controlled once. Relays are electrically operated control switches, and are classified according to their use as POWER RELAYS or CONTROL RELAYS. Power relays are called CONTACTORS, control relays are usually known simply as relays. The function of a tieor is to use a relatively small amount of electrical power to control the switching of a large amount of power. Control relays are frequently used in the control of low power circuits. . 4. 2 Electro magnetised Relay Relays in which the relative movements of their mechanical components produce preset responses under the effect of the current in the input circuit are called electromagnetic relays. The relay used in this project is electromagnetic relay which is shown in figure 6. 4. 2. Figure 6. 3 Electromagnetic Relay 6. 4. 3 Operation OperationAndWhen a certain voltage or current is applied to both ends of the coil of an electromagnetic relay, the magnetic flux passes through the magnetic circuit constitute of squeeze core, yoke press out, armature beseech and the magnetic circuit operation air gap.Under the influence of magnetic field, armature iron is attracted to iron core pole face thus propelling commonly closed in(p) contact to open and normally open contact to close, when the applied voltage or current at both ends of the coil is glare than a certain value and mechanical reactance is greater than electromagnetic attraction, armature iron is restored to the original state and normally open contact opens and normally closed contact closes. 6. 4. 4 Components of Electromagnetic Relay Electromagnetic relay is composed of magnetic circuit system, contact system and return mechanism.Magnetic circuit system is made up of such part as iron core, yoke iron, armature iron and coil. Contact system is composed of such parts as static contact spring, movable contact spring and contact seat. Return mechanism is made up of return springs of draw springs. Figure 6. 4 Components of Elect romagnetic Relay 6. 5 Devices The devices include microwave oven, electric bulbs, fans, motors, coolers, etc. Any of the devices can be operated from anywhere by interfacing them to the microcontroller. CHAPTER 7 COMPONENTS INTERFACING WITH MICROCONTROLLER 7. MT8888C Interfacing With Microcontroller The MT8888 DTMF transceiver is interfaced to the microcontroller port P2. The data pins of transceiver are interfaced with P2. 0-P2. 3 and the control pins are connected to P2. 4-P2. 7 as shown in figure 7. 1. PHILIPS 89C51MT8888 Figure 7. 1 Interfacing MT8888 with the microcontroller 7. 2 LCD Interfacing with the Microcontroller Depending on how many lines are used for connection to the microcontroller, there are 8bit and 4bit LCD modes. The appropriate mode is determined at the beginning of the process in a phase called initialization.In the first case, the data are transferred through outputs D0-D7 as it has been already explained. In case of 4-bit LED mode, for the sake of saving val uable I/O pins of the microcontroller, there are only 4 higher bits (D4-D7) used for communication, while other may be left unconnected. Consequently, each data is sent to LCD in two move four higher bits are sent first (that normally would be sent through lines D4-D7), four take down bits are sent afterwards. With the help of initialization, LCD will correctly connect and interpret each data received.Besides, with regards to the fact that data are seldom read from LCD (data in the main are transferred from microcontroller to LCD) one more I/O pin may be saved by straightforward connecting R/W pin to the Ground. Such saving has its price. Even though message displaying will be normally performed, it will not be possible to read from busy flag since it is not possible to read from display. Here we used 8 bit LCD. The LCD is interfaced with microcontroller port P0. The data pins of LCD are interfaced with the Port 0 pins P0. 0-P0. 7 and the control pins of LCD are interfaced with Port 1 pins P1. -P1. 7 as shown in figure 7. 2. PHILIPS 89C51 LCD Figure 7. 2 Interfacing LCD to the Microcontroller Algorithm to send data to LCD 1. Make R/W low 2. Make RS=0 if data byte is command RS=1 if data byte is data (ASCII value) 3. Place data byte on data register 4. Pulse E (HIGH to LOW) 5. Repeat the steps to send another data byte 7. 3 Interfacing devices with the microcontroller The devices that are to be controlled are interfaced with port 1 of microcontroller. Here we used four devices and they are interfaced to P1. 0-P1. 3 as shown in figure 7. 3.Figure 7. 3 Interfacing devices with the microcontroller CHAPTER 8 packet DETAILS 8. 1 Keil Vision 4 Keil was founded in 1986 to market the stick on products for development tools provided by many of the silicon vendors. Keil implemented the first C compiling program designed from the ground up specifically for 8051 microcontroller. Keil provides broad range of development tools like ANSI C Compiler, macro assembler, deb uggers and simulators, linkers, IDE library managers, real time operating system &038 evaluation boards for 8051 &038 ARM families. It is used to write programs for an application.The programs can be written in implant C or in assembly language. 8. 1. 1 Evaluation of Keil Software Start the Vision Program Select new Vision Project from the project bill Give the project name prjname and save it with extension*. uvproj as shown in fig 8. 1. 1a After saving another window will be displayed to select the stooge device. In that select LPC 2478 from NXP (founded by Philips) from the data base given Select it and click OK a new project with scratch cross-file will be created. Select the new from the file identity card Type your c file Select save from file menu.The first time you save the program a dialog box will pop-up and allow you to name your file and file type. Save program with file name xxxx. c The file type mentioned at last (. c) means embedded c language. Right click on sou rce group and click add files to source group. This will add files to project as shown in figure 8. 1. 1(b) Right click on source group and select build all target files. This will create delight file needed for ARM. Figure 8. 1 Starting a sensitive Project in KEIL Figure 8. 1 indicates how to start a new project in KEIL software to develop a program. Select the name of the project ant save it as . v2, then a new project is created as shown in figure. Figure 8. 2 Adding Files to the Source Group Figure 8. 2 shows how we should add files to the source group after we created a new project using KEIL micro vision. Figure 8. 3 Program written in the File added to the Source Group Figure 8. 3 shows the picture after the program file is being added to the source group so that an ASM file is created for the source file where code is written. 8. 1. 2 utilise the Keil dscope Debugger Select start /stop debug academic session from debug menu The debug program will start a new session as s hown in figure 8. 1. 1(d) SelectFile, load object file from the program menu. Change the file type to HEX Select your ravish file, e. g. xxxx. Hex Click OK You should now see the source code of the file typed in earlier Select Peripherals, GPIO Fast Interface, Ports required from the program menu. So that you can see the how output varies on ports. Select Port 0, Port 1, Port 2, Port 3 and port 4. Select Peripherals, UART, UARTs required from the program menu. So that you can see the how output varies on UARTs. Select UART0, UART1, UART2 and UART3. Click on go to see the real time update of the I/O ports. Click on stop when you are finished.You can also single step through you program or set break points at locations that you want the debugger to stop at. To set a breakpoint, double click on the line. Figure 8. 4 Debugging the code using Start/Stop Debug Session Figure 8. 4 shows that after the ASM file is created, it should be debugged using Start/Stop Debug Session. The program d ebuuging starts when we press the start and it can be ended using stop. Figure 8. 5 After Debugging, the value of the registers 8. 2 Flash Magic Software The trice magic software is one of the best known microcontroller programs dumping software.It has the compatibility with the KEIL software. The HEX file generated by the KEIL is used by the FLASH MAGIC to program the microcontroller. The software uses the computer serial port to transmit data into microcontroller. It has many options like appending the code, erasing the memory, reading from the microcontroller etc to dump the code program first the FLASH MAGIC has to be provided with necessary information about the target, the band rate supported, the clock frequency,etc. ,then the software checks for the device connected to the computer serial port.If the target is not connected, an error is generated. The software then checks for the available memory and the size of file to be dumped. Then it checks whether the target (microcon troller) is in ISP (In system programming) mode or not. If everything is fine then, it starts writing into the microcontroller using the serial data transfer pins Txd and Rxd pins on the microcontroller. After the code is loaded into the microcontroller, even the power goes off , the code will not be lost as it is stored in the EEPROM which is not volatile. Giving the RESET will restart the program execution from the beginning.We have seen that using a high level language improves the readability of the program, makes the programming process more efficient, and makes it possible to write portable code. The compiler generates the assembly code and therefore places a large role in determining the actual CPU operation. Because compilers are not as smart as programmers are, the machine code generated by compiler if typically larger and less efficient than the machine code generated from assembly source code. This may be disconcerting to some programmers, but it is not a good enough re ason to avoid high level languages.Instead, it means that you must know yourcompiler and know how the different parts of your C code will be implemented. Figure 8. 2 Flash Magic for dumping the code into the microcontroller Flow Chart NO YES YESYES NO YES YES NO YESYES NO YESYES NO 8. 4 Source Code /***DTMF REMOTE APPLIANCE CONTROL dodge USING MOBILE PHONE***/ /***************************** hand A2***********************************/ /********DTMF INITIALISATION********/ Dtmf_data equ p2 Dtmf_wr equ p2. 7 Dtmf_cs equ p2. 6 Dtmf_rs0 equ p2. 4 Dtmf_rd equ p2. 5 /********LCD INITIALISATION*********/ liquid crystal displaydata equ p0 Lcd_rs equ p1. 5 Lcd_rw equ p1. 6Lcd_en equ p1. 7 /*******DEVICES INITIALISATION********/ dev1 equ p1. 0 dev2 equ p1. 1 dev3 equ p1. 2 dev4 equ p1. 3 psswrd bit 21 org 00h mov p1,0f0h mov r0,50h call Dtmf_init call Lcd_init /*call DispLine1 mov dptr,Proj_name call Disp_string call delay call DispLine2 mov dptr,Proj_name1 call Disp_string call delay call D ispLine3 mov dptr,Proj_name2 call Disp_string call delay call Clr_Display call DispLine1 mov dptr,College_name call Disp_string call delay call Clr_Display call DispLine2 mov dptr,College_location call Disp_string call delay call Clr_Display call DispLine1 mov dptr,TEAM call Disp_string call DispLine2 ov dptr,NAME1 call Disp_string call DispLine3 mov dptr,NAME2 call Disp_string call delay call Clr_Display call DispLine1 mov dptr,NAME3 call Disp_string call DispLine2 mov dptr,NAME4 call Disp_string call DispLine3 mov dptr,NAME5 call Disp_string call DispLine4 mov dptr,NAME6 call Disp_string call delay call Clr_Display */ main call Clr_Display mov dptr,myname call Disp_string clr psswrd Rx_tone mov a,8fh call Lcd_cmnd mov r0,50h mov r7,00h store_tone call delay50ms clr a call read_sta_reg jnb acc. 2,store_tone call read_rx_data_reg anl a,0fh jb psswrd, match mov r0,a mov a,* call Lcd_data_out inc r0 inc r7 jne r7,04,store_tone mov r0,50h mov a,r0 cjne a,1,invalid_Tone inc r0 mov a,r0 cjne a,2,invalid_Tone inc r0 mov a,r0 cjne a,3,invalid_Tone inc r0 mov a,r0 cjne a,4,invalid_Tone call Clr_Display mov dptr,yesOk call Disp_string setb psswrd jmp store_tone invalid_Tone call Clr_Display mov dptr,NotOk call Disp_string clr psswrd call delay50ms call delay50ms jmp main /***********************************************/ compare cjne a,01,label1 setb dev1 call Clr_Display call DispLine1 mov dptr,labela call Disp_string setb psswrd jmp store_tone label1cjne a,02,label2 setb dev2 call Clr_Display call DispLine2 mov dptr,labelb all Disp_string setb psswrd jmp store_tone label2cjne a,03,label3 setb dev3 call Clr_Display call DispLine3 mov dptr,labelc call Disp_string setb psswrd jmp store_tone label3cjne a,04,label4 setb dev4 call Clr_Display call DispLine4 mov dptr,labeld call Disp_string setb psswrd jmp store_tone label4cjne a,05,label5 clr dev1 call Clr_Display call DispLine1 mov dptr,labele call Disp_string setb psswrd jmp store_tone label5cjne a,06,label6 clr dev2 call Clr_Display call DispLine2 mov dptr,labelf call Disp_string setb psswrd jmp store_tone label6cjne a,07,label7 clr dev3 call Clr_Display call DispLine3 mov dptr,labelg all Disp_string setb psswrd jmp store_tone label7cjne a,08,label8 clr dev4 call Clr_Display call DispLine4 mov dptr,labelh call Disp_string setb psswrd label8 jmp store_tone /*&8212&8212&8212&8212-Dtmf_init&8212&8212&8212&8212&8212&8212&8212-*/ Dtmf_init call read_sta_reg mov a,00h call write_cnt_reg mov a,00h call write_cnt_reg mov a,08h call write_cnt_reg mov a,00h call write_cnt_reg call read_sta_reg ret read_sta_reg mov Dtmf_data,0ffh setb Dtmf_rs0 setb Dtmf_wr clr Dtmf_rd clr Dtmf_cs nop nop mov a,Dtmf_data setb Dtmf_cs setb Dtmf_rd ret write_cnt_reg mov Dtmf_data,a setb Dtmf_rd clr Dtmf_wr setb Dtmf_rs0 clr Dtmf_cs nop nop etb Dtmf_cs setb Dtmf_wr ret read_rx_data_reg mov Dtmf_data,0ffh clr Dtmf_rs0 setb Dtmf_wr clr Dtmf_rd clr Dtmf_cs nop nop mov a,Dtmf_data setb Dtmf_cs setb Dtmf_rd ret /***********Lcd Display *******************/ Lcd_init mov a,30h call Lcd_cmnd mov a,38h call Lcd_cmnd mov a,06h call Lcd_cmnd mov a,0ch call Lcd_cmnd mov a,01h call Lcd_cmnd ret Lcd_cmnd call delay_50ms mov Lcddata,a clr Lcd_rs clr Lcd_rw setb Lcd_en nop nop clr Lcd_en ret Lcd_data_out call delay_50ms mov Lcddata,a setb Lcd_rs clr Lcd_rw setb Lcd_en nop nop clr Lcd_en ret Disp_string clr a movc a,a+dptr jz congest call delay_50ms call Lcd_data_out nc dptr jmp Disp_string exitret /*****************************************************/ /*****************************************************/ routine for clearing display Clr_Display mov a,01h call lcd_cmnd ret /****************************************************/ /****************************************************/ this routine is for display in different lines DispLine1 mov a,80h call LCD_Cmnd ret DispLine2 mov a,0C0h call LCD_Cmnd ret DispLine3 mov a,94h call LCD_Cmnd ret DispLine4 mov a,0D4h call LCD_Cmnd ret /******************************************* **********/ delay call Delay50ms call Delay50ms all Delay50ms call Delay50ms call Delay50ms ret delay50ms mov r2,5 back2mov r1,200 back1mov r5,250 backdjnz r5,back djnz r1,back1 djnz r2,back2 ret delay_50ms mov r4,20 back4mov r3,250 back3djnz r3,back3 djnz r4,back4 ret /*&8212&8212&8212&8212&8212&8212&8212&8212&8212&8212&8212&8212-*/ Display String data Proj_name DB DTMF REMOTE APPLIANCE ,0 Proj_name1 DBCONTROL SYSTEM, 0 Proj_name2DBUSING MOBILE PHONE, 0 College_nameDB MIC COLLEGE OF TECHNOLOGY , 0 College_location DB KANCHIKACHERLA , 0 TEAMDB DEVELOPED , 0 NAME1 DB BY , 0 NAME2 DB A2 BATCH , 0NAME3 DB LAVANYA , 0 NAME4 DB SIRISHA , 0 NAME5 DB pavane KUMAR , 0 NAME6 DB KISHORE , 0 myname DB ENTER PASSWORD,0h yesOk DB VALID PASSWORD,0h NotOk DB INVALID PASSWORD, 0h labeladb DEVICE1 ON ,0 labelbdb DEVICE2 ON ,0 labelcdb DEVICE3 ON ,0 labelddb DEVICE4 ON ,0 labeledb DEVICE1 OFF ,0 labelfdb DEVICE2 OFF ,0 labelgdb DEVICE3 OFF ,0 labelhdb DEVICE4 OFF ,0 end CHAPTER 9 ADVA NTAGES &038 APPLICATIONS 9. 1 Advantages Increased productivity Low cost Reduces power consumption Virtual control of appliances High security 9. Disadvantages No acknowledgement Switch-device pair should be known Network failure 9. 3 Applications Other applications of this circuit include Agriculture Industry Colleges Schools Future sweetening Acknowledgement of the devices initial condition through SMS. This system can be expanded to provide control over the GPRS. closure This project DTMF REMOTE APPLIANCE CONTROL SYSTEM USING MOBILE PHONE overcomes the limitations of Wireless Domestic Automation which uses a transmitter and receiver to control the home appliances. It resembles a virtual human controlling the remote appliances using a control unit and a mobile phone.It mainly uses DTMF transceiver for decoding the tones generated by the mobile phone, which is given to the micro-controller to control the appliances. The remote appliances control system using mobile phone will one day become a reality and it may revolutionize our way of living. The wide areas of application include controlling the appliances like microwave oven, lighting fans, lights, etc. Another major application is industrial automation as it reduces the power consumption and is of low cost. As this system is implemented using in 2G communication network, the video data cannot be obtained.Future work includes research on the robot control system in 3G communication networks which facilitates controlling the remote robot using DTMF of mobile phone, with video data from the remote mobile robots camera. The Future enhancement also includes control of GPRS system using this system. REFERENCES Text Books The 8051 Micro Controller architecture and embedded systems by Mazidi and Mazidi. Other References www. atmel. com www. alldatasheets. com www. electronicshub. com www. philips. com International Journal of Electrical &038 Computer Sciences IJECS Vol 9 No 10